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TD351
Advanced IGBT/MOSFET Driver
s s s s s s 1A sink / 0.75A source min. gate drive Active Miller clamp feature Adjustable and accurate two steps turn-off level and delay Input compatible with pulse transformer or optocoupler UVLO protection 2kV ESD protection
N DIP-8 (Plastic Package)
Description
TD351 is an advanced gate driver for IGBT and power MOSFET. Control and protection functions are included and allow the design of high reliability systems Innovative active Miller clamp function avoids the need of negative gate drive in most applications and allows the use of a simple bootstrap supply for the high side driver TD351 includes a two-level turn-off feature with adjustable level and delay. This function protects against excessive overvoltage at turn-off in case of overcurrent or short-circuit condition. Same delay is applied at turn-on to prevent pulse width distortion. TD351 is compatible with both pulse transformer and optocoupler signals.
D SO-8 (Plastic Micropackage)
Pin Connections (top view)
IN VREF CD LVOFF
1 2
8 7
VH OUT VL CLAMP
TD351
3 4 6 5
Applications
s s s 1200V 3-phase inverter Motor control systems UPS
Order Codes
Part Number TD351IN TD351ID TD351IDT Temperature Range -40C, +125C Package DIP SO SO Packaging Tube Tube Tape & Reel Marking TD351I TD351I TD351I
November 2004
revision 1
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TD351 1 Block Diagram
Block Diagram
Figure 1: System and internal block diagram
16V
VH
IN VREF CD LVOFF
UVLO Control Block
VH OUT VL CLAMP
Vref Delay Off Level
VH
TD351
Table 1: Pin Description Name
IN VREF CD LVOFF CLAMP VL OUT VH
Pin Number
1 2 3 4 5 6 7 8
Type
Analog input Analog output Timing capacitor Analog input Analog output Power supply Analog output Power supply Input +5V reference voltage Turn on/off delay Turn off level Miller clamp Signal ground Gate drive output Positive supply
Function
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Absolute Maximum Ratings 2 Absolute Maximum Ratings
TD351
Table 2: parameters and their absolute maximum ratings Symbol
VHL Vout Vter Pd Tstg Tj Rhja ESD
Parameter
Maximum Supply Voltage (VH - VL) Voltage on OUT, CLAMP, LVOFF pins Voltage on other pins (IN, CD, VREF) Power dissipation Storage temperature Maximum Junction Temperature Thermal Resistance Junction-Ambient Electrostatic discharge
Value
28 VL-0.3 to VH+0.3 -0.3 to 7 500 -55 to 150 150 150 2
Unit
V V V mW C C C/W kV
Table 3: Operating Conditions Symbol
VH Toper
Parameter
Positive Supply Voltage vs. VL Operating Free Air Temperature Range
Value
UVLO to 26 -40 to 125
Unit
V C
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TD351 3 Electrical Characteristics
Electrical Characteristics
Table 4: Electrical characteristics for Tamb = -20 to 125C, VH=16V (unless otherwise specified) Symbol Parameter Test Condition Min
0.8 100 IN input voltage < 4.5V T=25C 4.85 10 5.00
Typ
1.0 4.0 135
Max
Unit
V V ns A V mA V V V
Input Vton IN turn-on threshold voltage Vtoff IN turn-off threshold voltage tonmin Minimum pulse width Iinp IN Input current Voltage reference - Note 1 Vref Voltage reference Iref Maximum output current Clamp Vtclamp CLAMP pin voltage threshold VCL Clamp low voltage Delay Vtdel Voltage threshold Rdel Discharge resistor Off Level Iblvoff LVOFF peak input current (sink) Violv Offset voltage Outputs Isink Output sink current Isrc Output source current VOL1 Output low voltage 1 VOL2 Output low voltage 2 VOH1 Output high voltage 1 VOH2 Output high voltage 2 tr Rise time tf Fall time (2 step turn-off disabled) tdon tdoff Turn on propagation delay Turn off propagation delay (2-level turn-off disabled) Input to output pulse distortion
4.2 220 1 5.15
2.0 Icsink=500mA 2.5 I=1mA LVOFF=12V LVOFF=12V Vout=6V Vout=VH-6V Iosink=20mA Iosink=500mA Iosource=20mA Iosource=500mA CL=1nF, 10% to 90% CL=1nF, 90% to 10% 10% output change: Rd=4.7k, no Cd Rd=10k, Cd=220pF 10% output change 10% output change, tw=Twout-Twin 10 9 0.5 90 -0.15 1700 1300 0.35 2.5 VH-2.5 VH-4.0 100 100 600 2.2 550 50 100 500 200 0 2.5
-0.3 1000 750
A V
mA mA V V V V ns ns ns s ns ns
1.8
2.0
tw
Under Voltage Lockout (UVLO) UVLOH UVLO top threshold UVLOL UVLO bottom threshold Vhyst UVLO hysteresis Supply current Iin Quiescent current
Vhyst=UVLOH-UVLOL input low, no load
11 10 1
12 11
V V V mA
2.5
Note: 1.Recommended capacitor range on VREF pin is 10nF to 100nF
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Functional Description 4 Functional Description 4.4 Two level turn-off
TD351
4.1 Input stage
TD351 input is compatible with optocouplers or pulse transformers. The input is triggered by the signal edge and allows the use of low-sized, lowcost pulse transformer. Input is active low: output is driven high when input is driven low. The IN input is internally clamped at about 5V to 7V. When using an open collector optocoupler, the resistive pull-up resistor can be connected to either VREF or VH. Recommended pull-up resistor value with VH=16V are from 4.7k to 22k. When driven by a pulse transformer, the input positive and negative pulse widths at the Vton and Vtoff threshold voltages must be larger than the minimum pulse width tonmin (see fig. 4). This feature acts as a filter against invalid input pulses smaller than tonmin.
During turn-off, gate voltage can be reduced to a programmable level in order to reduce the IGBT current (in the event of over-current). This action avoids both dangerous overvoltage across the IGBT, and RBSOA problems, especially at short circuit turn-off. Turn-off (Ta) delay is programmable through external resistor Rd and capacitor Cd for accurate timing. Ta is approximately given by: Ta (s) = 0.7. R d (kOhms). Cd (nF) Turn-off delay (Ta) is also used to delay the input signal to prevent distortion of input pulse width. The Two level turn-off sequence can be disabled by connecting LVOFF pin to VH and connecting CD pin to VREF with a 4.7k resistor.
4.5 Minimum Input ON-time
Input signals with ON-time smaller than Ta are ignored. ON-time signals larger than Ta+2.Rdel.C d (Rdel is the internal discharge switch resistance, Cd is the external timing capacitor) are transmitted to the output stage after the Ta delay with minimum width distortion (Tw=Twout-Twin). For ON-time input signals close to Ta (between Ta and Ta+2.Rdel.Cd), the 2-level duration is slightly reduced and the total output width can be smaller than the input width (see fig. 5).
4.2 Voltage reference
A voltage reference is used to create accurate timing for the turn-on delay with external resistor and capacitor. The same circuitry is also used for the two-level turn-off delay. A decoupling capacitor (10nF to 100nF) on VREF pin is required to ensure good noise rejection.
4.3 Active Miller clamp:
The TD351 offers an alternative solution to the problem of the Miller current in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to increase the safety margin, the TD351 uses a dedicated CLAMP pin to control the Miller current. When the IGBT is off, a low impedance path is established between IGBT gate and emitter to carry the Miller current, and the voltage spike on the IGBT gate is greatly reduced. During turn-off, the gate voltage is monitored and the clamp output is activated when gate voltage goes below 2V (relative to VL). The clamp voltage is VL+4V max for a Miller current up to 500mA. The clamp is disabled when the IN input is triggered again. The CLAMP function doesn't affect the turn-off characteristic, but only keeps the gate to the low level throughout the off time. The main benefit is that negative voltage can be avoided in many cases, allowing a bootstrap technique for the high side driver supply.
4.6 Output stage
The output stage is able to sink/source 1.7A/1.3A typical at 25C and 1.0A/0.75A min. over the full temperature range. This current capability is specified near the usual IGBT Miller plateau.
4.7 Undervoltage protection
Undervoltage detection protects the application in the event of a low VH supply voltage (during startup or a fault situation). During undervoltage, the OUT pin is driven low (active pull-down for VH>2V, passive pull-down for VH<2V.
UVH VH UVL Vccmin
2V OUT
FAULT
5/12
TD351
Figure 2: Detailed internal schematic
Functional Description
UVLO
Comp_Input
IN
7V
Filter
1V-4V
VREF
5V Vref
Comp_DelayOff
Control Block
CD
2.5V
S2
Comp_Clamp
CLAMP
2V
VH
OUT
LVOFF
90uA
2-level OFF driver
VL
rev. 2
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Timing Diagrams 5 Timing Diagrams
TD351
Figure 3: General turn-on and 2-level turn-off sequence
Twin IN
COFF Ta VH level LVOFF OUT VL level Ta
Twout Open
CLAMP VH level Miller plateau Vge VL level Clamp threshold
Vce
Figure 4: input and output waveform dynamic parameters
Twin IN (level mode) Vton tonmin Vtoff Vton Vtoff
IN (edge mode) tonmin
VH level LVOFF OUT tdon tdoff Twout VL level
Figure 5: Minimum ON-time
Tin(Ta+2.Rdel.Cd)
2.5V CD Ta 7/12
TD351 6 Typical Performance Curves
Typical Performance Curves
Figure 6: Quiescent current vs temperature
2.5 2.0 In (mA) 1.5 1.0 0.5 0.0 -50 -25 0 25 50 75 100 125 Temp (C)
Figure 9: Rdel resistance vs temperature
500 400 Rdel (Ohms) 300 200 100 0 -50 -25 0 25 50 75 100 125 Temp (C)
Figure 7: Low level output voltage vs temp.
3.0
Figure 10: High level output voltage vs temp.
4.0
3.0 VH-VOH (V)
VOL-VL (V)
2.0
Iosink=500mA
Iosource=500mA
2.0
1.0
1.0
Iosource=20mA
Iosink=20mA
0.0 -50 -25 0 25 50 75 100 125 Temp (C)
0.0 -50 -25 0 25 50 75 100 125 Temp (C)
Figure 8: Sink current vs temperature
2000 1800 Isink (mA) 1600 1400 1200 1000 -50 -25 0 25 50 75 100 125 Temp (C)
Figure 11: Source current vs temperature
1600
1400 Isrc (mA)
1200
1000
800 -50 -25 0 25 50 Temp (C) 75 100 125
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Application Diagrams 7 Application Diagrams
TD351
Figure 12: Single supply IGBT drive with active Miller clamp
16V
VH
4.7k
IN VREF CD LVOFF
UVLO Control Block
VH OUT VL CLAMP
Vref Delay Off Level
VH
TD351
Figure 13: Use of pulse transformer signals
16V
ransfo
IN VREF CD LVOFF
UVLO Control Block
VH OUT VL CLAMP
Vref Delay Off Level
VH
TD351
Figure 14: Large IGBT drive with negative voltage gate drive and optional current buffers
VH
4.7k
IN 16V VREF CD LVOFF
UVLO Control Block
VH OUT VL CLAMP
Optional
Vref Delay Off level
-10V
VH
TD351
Optional
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TD351
8 Package Mechanical Data
Package Mechanical Data
8.1 DIP-8 Package
Plastic DIP-8 MECHANICAL DATA
mm. DIM. MIN. A a1 B B1 b b1 D E e e3 e4 F I L Z 0.44 3.3 1.6 0.017 8.8 2.54 7.62 7.62 7.1 4.8 0.130 0.063 0.38 0.7 1.39 0.91 0.5 0.5 9.8 0.346 0.100 0.300 0.300 0.280 0.189 0.015 1.65 1.04 TYP 3.3 0.028 0.055 0.036 0.020 0.020 0.386 0.065 0.041 MAX. MIN. TYP. 0.130 MAX. inch
P001F
10/12
Package Mechanical Data 8.2 SO-8 Package
TD351
SO-8 MECHANICAL DATA
DIM. A A1 A2 B C D E e H h L k ddd 0.1 5.80 0.25 0.40 mm. MIN. 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 0.228 0.010 0.016 TYP MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.04 0.043 0.013 0.007 0.189 0.150 0.050 0.244 0.020 0.050 inch TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157
8 (max.)
0.04
0016023/C
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TD351 9 Revision History
Date 01 Nov 2004 Revision 1 First Release Description of Changes
Revision History
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved
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